This invention relates to an integrated circuit, and particularly relates to an art such that a field programmable gate array (FPGA) performs functions as a central processing unit (CPU) core and a peripheral device thereof.
Conventionally, as to a logic integrated circuit (IC), there have been known a general-purpose logic IC and an application specific IC (ASIC). The general-purpose logic IC, which can be mass-produced, and cost-effective, includes devices functions of which are completed by users by themselves, such as a microprocessor, a programmable logic device (PLD). As to said PLD, there have been a programmable logic array (PLA), an FPGA, and the like. In the FPGA, the user places logic module configured by a basic logic circuit and unconnected wiring to a chip, and completes the wiring with program elements, thereby obtaining a desired function. The microprocessor is generally called a system large-scale integration (LSI) in that a CPU is integrated on an LSI chip, and embodied as a combination of a logic circuit and a memory circuit. Further, as to this kind of microprocessor, there has been known an RISC (reduced instruction set computer) in which high performance is achieved by simplifying command processing and hardware.
However, predetermined functions are previously integrated in the above-mentioned microprocessor which includes a general-purpose CPU core, and users use limited functions among them, wherein it is difficult to change the configuration in order to serve specific purposes. Furthermore, the microprocessor is configured by a CPU core and a number of chips, which complicates the configuration with many implemented components, so that problems have arisen in reliability.
This invention is made to solve the above-mentioned problems. One object of the present invention is to provide an integrated circuit as an RISC processor, wherein an FPGA itself has functions as a CPU core, and includes a user""s circuit and the like, thereby performing as a system LSI having functions desired by users without employing a conventional CPU core, and wherein implemented components such as chips of peripheral circuits are decreased in number, thereby allowing costs to be reduced.
In order to achieve the above-mentioned objects, the present invention provides an integrated circuit equipped with a field programmable gate array and a memory device, wherein a CPU core and peripheral circuits connected thereto are stored as logic data in the memory device, and wherein the field programmable gate array performs functions as the CPU core and the peripheral circuits based on contents stored in the memory device.
In the above, functions of the CPU core and peripheral circuits can be changed according to the logic data stored in the memory device, which allows a system LSI to be designed easily. Furthermore, since the field programmable gate array performs functions as the CPU core and peripheral circuits, the number of chips to be implemented is decreased.
The above-mentioned constitution can be constructed such that the peripheral circuits include a system bus to which a user can connect an arbitrary circuit. Therefore, the user can readily extend and change functions of the CPU core by retrofitting a desired circuit.
Further, the above-mentioned configuration can be constituted such that the arithmetic processing performed by the CPU core has a structure that a dummy step is incorporated into steps of fetch, decode, execution, memory and write-back, wherein these steps are divided into three stages: a first stage for carrying out in order of fetch and decode, a second stage for carrying out in order of execution and memory, and a third stage for carrying out in order of dummy and write-back, wherein the processing is carried out in order of first, second and third stages, and wherein, every time one stage is completed, another arithmetic processing is started, and simultaneous operations of different arithmetic processing are executed parallel in the three-stage pipeline construction. In this configuration, in the parallel operation of multiple arithmetic processing, the fetch cycle and memory cycle are not simultaneously carried out, and generates no situation in which these cycles compete with each other for a same memory. Therefore, this configuration can perform the parallel processing without a cash memory.
Furthermore, according to the present invention, a computer readable recording medium has data to be written in a recording device of an integrated circuit, composed of a field programmable gate array and a memory device. The data is logic data for making the field programmable gate array perform functions as the CPU core and peripheral circuits connected to the CPU core.
The above-mentioned constitution makes it possible to easily design a system LSI such that a computer reads out the data in the recording medium, and the field programmable gate array performs functions as the CPU core and peripheral circuits thereof in the computer.
According to the above-mentioned configuration, a computer-readable recording medium includes a system bus in peripheral circuits, wherein a user can connect an arbitrary circuit to the system bus.
Furthermore, in the above, the logic data includes a configuration in which arithmetic processing executed by the CPU core has a structure that a dummy step is incorporated into steps of fetch, decode, execution, memory and write-back, wherein these steps are divided into three stages: a first stage for carrying out in order of fetch and decode, a second stage for carrying out in order of execution and memory, and a third stage for carrying out in order of dummy and write-back, wherein the processing is carried out in order of first, second and third stages, and wherein, every time one stage is completed, another arithmetic processing is started, and simultaneous operations of different arithmetic processing are executed parallel in the three-stage pipeline construction.